Introduction

Along with the adoption of PCI Express® into mobile and storage systems such as SFF-8639 and M.2 (NGFF) form factors, there is also a need for protocol-level probing capabilities of these devices.

Teledyne LeCroy offers comprehensive probing solutions used in conjunction with a variety of PCIe® analyzers to allow advanced traffic decoding, filtering, triggering and recording. Interposer probe cards are installed between the root complex at the host side and the end-point or add-in card to sample PCIe signals passively via tapping resistors followed by limiting amplifier stage to the analyzer.

An active interposer using either linear or limiting splitters regenerates and equalizes the signals before forwarding them to the system under test (SUT) and the analyzer. Teledyne LeCroy offers interposer-based probes not only for standard PCIe slot connectors, but also for other form factors, such as VPX, XMC, AMC, Mini-card and compact PCI (see note 1), as well as others in development.

The mid-bus probe, which falls under the category of passive probe, is used for chip-to-chip probing in which the probe is installed to make contact with a dedicated set of footprints and retention module on the SUT. All of these probing options are extensively used by OEMs worldwide, but there is a unique challenge associated with probing PCIe links on a mobile device, namely the lack of board real estate to accommodate a mid-bus footprint or interposer card due to space constraints.

While Teledyne LeCroy offers many custom interposers that fit specific form factors, there has been a growing interest in the PCIe community to use a multi-lead (or soldered-down) probe similar to that used for oscilloscopes. There are at least three benefits of using soldered-down protocol probes:

First, no extra board area on the SUT is necessary. Since the probe tips can be attached at flexible locations along the PCIe channels, there is no need for a specific set of footprints like that of the mid-bus probe.

Second, there is minimal mechanical interference, unlike that in the interposer-based scenario in which the add-in card often ends up being installed outside the chassis and extra mechanical support is needed.

Third, the soldered-down probe is less intrusive electrically. Other than extracting a small portion of energy from the channels under test, the probe does not introduce extra interconnect loss and signal distortion in the SUT due to traces and connectors, unlike the interposer-based scenario.

The purpose of this article to provide some guidelines for using the Teledyne LeCroy PCIe Gen3 (see note 2) multi-lead probe for the best signal reception at the analyzer equipment to ensure the most reliable traffic capture quality. It consists of SUT-level optimization and proper probe-assembly installation techniques.

Selecting Optimal Probing Location

The first step, before installing the probe tip on the SUT, is to determine the optimal location mechanically and electrically. Figure 1 is a representation of a typical PCIe channel consisting of a transmitter (Tx), a DC blocking capacitor (Tx cap), transmission line and a receiver (Rx) in differential configuration. There may be additional elements comprising the transmission channel such as vias and/or connectors. A chip-to-chip connectivity scenario is when there is no connector between Tx and Rx. The arrows in figure 1 indicate possible locations to solder down the probe tip. Other potential locations not shown in the figure are connector pins and exposed vias along the transmission channel, although they are not recommended, since these locations are usually in the middle of the channel, where signal quality is the worst.

Figure 1:

A system diagram showing PCIe channel connectivity with potential protocol probing locations (shown by the arrows).

A general rule of thumb is that a desirable probing location should be mechanically accessible for probe tip installation and the signal quality is the best. The Tx and Rx ports may be accessible through vias located directly underneath or near the Tx and Rx BGAs.

Placement close to Tx has the benefit of strong signal, but the presence of excessive de-emphasis such as preset 7 with 6-dB de-emphasis and 3.5-dB pre-shoot may be less than optimal for the probe. The peaking due to de-emphasis and pre-shoot is attenuated somewhat at either side of Tx cap, a second possible optimal location that may offer a better signal.

The question is: “How do we determine which location gives the best signal?”

It can be done through channel simulation and comparison of the signal quality at various locations, but we recommend probing the signal directly at the locations shown in figure 1 using the Teledyne LeCroy 25-GHz soldered-down or browser probe (see note 3) and capturing the eye diagram using Teledyne LeCroy’s real-time high-speed oscilloscope (see note 4). While the Teledyne LeCroy PCIe Gen3 multi-lead probe has been shown to work with signals having as low as 42-mV differential eye height and 72-ps differential eye width as shown in figure 2 (taken from a customer SUT), it is recommended that the eye width and height at the probing location be 70 mV or greater and 75 ps or greater, as shown in figure 3, respectively, which in most cases is achievable at the Tx cap or BGA vias.

Figure 2: Sub-standard signal.

Figure 3: Desirable signal.

Figure 2 and figure 3: Examples of differential eye diagrams of a PCIe Gen3 signal captured at the connector pins on a SUT in which a Teledyne LeCroy multi-lead probe was installed.

There are two other factors to consider from the perspective of the SUT.

  • First, make sure that the SUT 100-MHz reference clock is fed to the clock input of the amplifier pod included in the multi-lead probe package via a standard three-pin clock cable that can be connected to a three-pin clock header on the SUT. Needless to say, the clock needs to be PCIe-compliant whether it is SSC-modulated or non-SSC.
  • Second, when possible, adjusting Tx preset level as well as the Tx voltage swing may result in a better signal at the probing location. This option requires manual change usually via BIOS or a GUI, and is not always possible. If the signals on the Tx side - whether they be at the Tx BGA or Tx cap - exhibit too much peaking, users may consider placing the probe at the Rx BGA side, assuming that the BGA vias are exposed and the eye diagram shows better width and height than those at the Tx side.

Probe Installation

Users may consider a few factors when installing Teledyne LeCroy PCIe3 multi-lead flex probe tips. First, what is a suitable length for a flex tip? Mechanically, the 6-inch tip may be more suitable since the amplifier pod connected to the tip can be placed farther away from the SUT, hence cause less interference. A 6-inch tip may also be better for damping excess peaking at the probe location due to a longer trace on the flex cable. When the probed signal is relatively weak, however, a shorter 3-inch tip may be necessary since it has a lower insertion loss than the 6-inch tip.

Second, users need to ensure that the wires at the end of the flex tip are soldered down on the SUT at an angle, preferably between 30° to 60° with respect to the SUT, as shown in figure 4. It is imperative that the wires not be placed parallel to the SUT board since the 90° wire bend will degrade signal integrity considerably.

Third, to reduce parasitic inductance, hence, to improve signal integrity, each wire can be cut short to about 30 mils from the initial length of 100 mils as shown in figure 5. Ideally, the shorter the wire the better, but mechanical considerations need to be taken into account. Flex tips with longer wires are more mechanically robust. When the wires are maintained at 100 mils when soldered on the SUT, users may consider adding low-loss RF non-conductive epoxy to strengthen the tip attachment to the SUT.

Fourth, the tip resistors on the flex tip, as shown in figure 6, can also be adjusted as an additional parameter that may improve signal integrity. The default tip resistor value is 250 Ω and the recommended resistance range is between 150 Ω to 300 Ω. Lower resistor values allow greater signal into the probe at the expense of greater channel loading. Higher resistor values result in less channel loading but also weaker signal to the probe which may be a better choice for signals with excessive peaking.

Figure 4:

A flex tip attachment in which the wires are placed at 30° to 60° with respect to the SUT board. In this picture, the angle is closer to 60°.

Figure 5:

A flex tip, the wires of which have been cut short by about a third of their original length.

Figure 6:

A soldered-down flex tip showing the 0201 package surface mount tip resistors.

Summary

The Teledyne LeCroy PCIe Gen3 multi-lead probe is the leading solution for probing PCIe links on mobile devices. This article provides best-practice recommendations to ensure robust and reliable traffic capture using Teledyne LeCroy PCIe analyzers. The two areas that users need to pay attention to are:

  • Choosing the probing location on the SUT.
  • Techniques for installing the flex tip that provide optimal signal quality.

Notes

Note 1:
Interposers and Probes

Note 2:
For guidelines for using Teledyne LeCroy PCIe Gen 1 and 2 soldered-down probes, see M. Dunn, A. Sutono, "Guidelines for Multi-Lead Probe Resistor Selection", Teledyne LeCroy Technical Brief, April 2013.

Note 3:
WaveLink® High Bandwidth Differential Probing System

Note 4:
SDA 8 Zi-A Serial Data Analyzers